Brainfuck CPU on FPGA with 3-stage pipeline and parallel execution

Brainfuck FPGA on FPGA

I have published a CPU that executes Brainfuck language directly on FPGA. CPU has 3-stage pipeline, and executes up to 4 commands (only +/- combination or </> combination) simultaneously.

The HDL files and project file

The code (Verilog-HDL) and the project file for Terasic DE-0 FPGA board are posted here.
https://github.com/moizumi99/brainf__k_CPU/tree/master/hdl

PIPELINE

I know it's not new to build a CPU on FPGA that executes brainfuck language. I am doing this for my hobby and fun. Also, I wanted to try out some things that I know only from text books. One of them is pipelining. I have implemented 3-stage pipepline into this CPU.

Stage-1: Fetch (PC increment, get operation from ROM)
Stage-2: Execute command (+/-/>/<)
Stage-3: Memory access (+/-/,: Write, >/</.: Read)

For loop ([]), the condition is checked in stage-1. The loop return address is stored in stack. The pipeline made the CPU speed about 3 times faster.

Parallel command execution

The next things I wanted to try was Super-Scaler. However, brainfuck language isn't build for that. So, I made the CPU execute multiple +/- commands and </> commands same time. It combines up to 4 such commands, and run in 1 cycle. This gave about 10% gain in the calculation of Pi. I am a bit puzzled why it was only 10%. Maybe Amdahl's law is taking place here, but still it doesn't add up.

Mapping of 360 degree image into a plane

I have been trying to find a way to map a 360 degree image from Ricoh Theta on to a plane, like a piece of paper. After several trial and error, I finally came up with something that I can tolerate.

If you take a look at a pixel, then move your eye to one direction, you can see that the scene is continuous except a finite number of singular points. This is an extension of regular 360 degree panorama photo.