Brainfuck FPGA on FPGA
I have published a CPU that executes Brainfuck language directly on FPGA. CPU has 3-stage pipeline, and executes up to 4 commands (only +/- combination or </> combination) simultaneously.The HDL files and project file
The code (Verilog-HDL) and the project file for Terasic DE-0 FPGA board are posted here.https://github.com/moizumi99/brainf__k_CPU/tree/master/hdl
PIPELINE
I know it's not new to build a CPU on FPGA that executes brainfuck language. I am doing this for my hobby and fun. Also, I wanted to try out some things that I know only from text books. One of them is pipelining. I have implemented 3-stage pipepline into this CPU.Stage-1: Fetch (PC increment, get operation from ROM)
Stage-2: Execute command (+/-/>/<)
Stage-3: Memory access (+/-/,: Write, >/</.: Read)
For loop ([]), the condition is checked in stage-1. The loop return address is stored in stack. The pipeline made the CPU speed about 3 times faster.